CCRB=00, CCRA=00, BD1=0, BD2=0, PR=00, CCRSWT=0
General PWM Timer Buffer Enable Register
| BD2 | GTCCR Buffer Operation Disable 0 (0): Enable buffer operation 1 (1): Disable buffer operation. |
| BD1 | GTPR Buffer Operation Disable 0 (0): Enable buffer operation 1 (1): Disable buffer operation. |
| Reserved | These bits are read as 00000000000000. The write value should be 00000000000000. |
| CCRA | GTCCRA Buffer Operation 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTCCRA <–> GTCCRC) 2 (10): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD) 3 (11): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD) |
| CCRB | GTCCRB Buffer Operation 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTCCRB <–> GTCCRE) 2 (10): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF) 3 (11): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF) |
| PR | GTPR Buffer Operation 0 (others): Setting prohibited 0 (00): Buffer operation is not performed 1 (01): Single buffer operation (GTPBR --> GTPR) |
| CCRSWT | GTCCRA and GTCCRB Forcible Buffer Operation This bit is read as 0. 0 (0): no effect 1 (1): Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. |
| Reserved | These bits are read as 000000000. The write value should be 000000000. |